1. Field
An embodiment discussed herein relates to correction of a duty ratio of a reference signal used for transmission inside or outside a large-scale integrated (LSI) chip.
2. Description of Related Art
Operating frequencies of components of information processing devices have increased, such as operation frequencies of computers, static RAMS (SRAMs), dynamic RAMs (DRAMs), processors, or LSIs for switches. Hence, an increase in signal transmission speed, for example, an increase in transmission capacity measured by bit per second (bps) and a decrease in transmission delay are desired.
A communication backbone device etc. may desirably have a high data rate for signal transmission/reception. As the amount of information for transmission/reception increases, the number of I/O channels on systems, substrates or chips increases.
A digital circuit performs data transfer in synchronization with a reference signal such as a clock signal. Accordingly, a circuit is designed so that a reference clock satisfies the strictest condition.
Related arts are disclosed in, for example, U.S. Pat. Nos. 7,015,739, 5,945,857, Japanese Laid-open Patent Publication No. 2007-329924, or the document of Digital Systems Engineering, William J. Dally, ISBN 0-521-59292-5, P606-607.